[NOTE ] coreboot-26.01rev1 Mon Sep 21 21:28:52 UTC 2026 x86_32 romstage starting (log level: 7)... [DEBUG] Disabling Watchdog reboot... done. [DEBUG] SMBus controller enabled [DEBUG] Setting up static northbridge registers... done. [DEBUG] Started PEG10 link training. [DEBUG] Initializing IGD... [DEBUG] Back from haswell_early_initialization() [DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i3-4150 CPU @ 3.50GHz [DEBUG] AES supported, TXT NOT supported, VT supported [DEBUG] PCH type: Q87, device id: 8c4e, rev id 5 [DEBUG] Starting native platform initialisation [INFO ] Intel ME early init [INFO ] Intel ME firmware is ready [DEBUG] ME: Checking whether CPU was replaced... not replaced [DEBUG] HSIO lane owner: 0x04 [DEBUG] SATA port enables: 0x3f [DEBUG] USB2 port 0 => disabled [DEBUG] USB2 port 1 => disabled [DEBUG] USB2 port 2 => mapped to OC pin 1 [DEBUG] USB2 port 3 => mapped to OC pin 2 [DEBUG] USB2 port 4 => mapped to OC pin 3 [DEBUG] USB2 port 5 => mapped to OC pin 3 [DEBUG] USB2 port 6 => mapped to OC pin 0 [DEBUG] USB2 port 7 => mapped to OC pin 0 [DEBUG] USB2 port 8 => mapped to OC pin 4 [DEBUG] USB2 port 9 => mapped to OC pin 4 [DEBUG] USB2 port 10 => mapped to OC pin 5 [DEBUG] USB2 port 11 => mapped to OC pin 5 [DEBUG] USB2 port 12 => mapped to OC pin 6 [DEBUG] USB2 port 13 => Invalid OC pin 7 for USB2 port 13 [DEBUG] USB3 port 0 => mapped to OC pin 6 [DEBUG] USB3 port 1 => mapped to OC pin 7 [DEBUG] USB3 port 2 => disabled [DEBUG] USB3 port 3 => disabled [DEBUG] USB3 port 4 => mapped to OC pin 1 [DEBUG] USB3 port 5 => mapped to OC pin 2 [DEBUG] Retraining DMI at Gen2 speeds... [DEBUG] DMI: Running at Gen1 x4 [DEBUG] DMI: Running at Gen1 x4 [INFO ] DMI: Running at Gen2 x4 [DEBUG] Programming SA DMI VC/TC mappings... [DEBUG] Programming PCH DMI VC/TC mappings... [DEBUG] Waiting for PCH DMI VC negotiation... done! [DEBUG] Waiting for SA DMI VC negotiation... done! [DEBUG] FMAP: area RW_MRC_CACHE found @ 400000 (65536 bytes) [INFO ] Using cached memory parameters [WARN ] Cannot fast boot: DIMMs have changed [ERROR] raminit failed on step RST_NONT [DEBUG] Found compatible clock / CAS settings [DEBUG] Selected DRAM frequency: 666 MHz [DEBUG] Selected CAS latency : 9T [DEBUG] MPLL busy... done in 9 us [DEBUG] MPLL frequency is set to: 666 MHz (period: 1501501 femtoseconds) [DEBUG] Quadrature clock period: 750 picoseconds [DEBUG] Selected tCK : 1500 ps [DEBUG] Selected tAA : 9T [DEBUG] Selected tWR : 10T [DEBUG] Selected tRCD : 9T [DEBUG] Selected tRRD : 4T [DEBUG] Selected tRP : 9T [DEBUG] Selected tRAS : 24T [DEBUG] Selected tRC : 33T [DEBUG] Selected tRFC : 174T [DEBUG] Selected tWTR : 5T [DEBUG] Selected tRTP : 5T [DEBUG] Selected tFAW : 20T [DEBUG] Selected tCWL : 7T [DEBUG] Selected tCMD : 2T [DEBUG] Selected tREFI : 5194T [DEBUG] Selected tXP : 4T [DEBUG] ME: Requested 0MB UMA [DEBUG] Stage 1: Vref offset training [DEBUG] Hi-Lo (XOR): [DEBUG] C0: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff [DEBUG] C1: 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff [DEBUG] RdVref: [DEBUG] C0: 1 1 0 1 0 0 1 1 [DEBUG] C1: 1 0 1 0 1 1 0 1 [DEBUG] Stage 2: Samp offset training [DEBUG] Channel 0 1 [DEBUG] Byte 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 [DEBUG] BitSAmp 76446748 55589655 89977987 65758786 8888a977 97868887 88775868 57568556 66656755 88898766 85567646 79778978 66576656 76776677 88878878 77867876 [DEBUG] Rank 0 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C0.R0: Left Right Width Center [DEBUG] B0: 280 336 56 308 [DEBUG] B1: 288 344 56 316 [DEBUG] B2: 304 360 56 332 [DEBUG] B3: 312 368 56 340 [DEBUG] B4: 320 376 56 348 [DEBUG] B5: 336 376 40 356 [DEBUG] B6: 344 400 56 372 [DEBUG] B7: 232 288 56 260 [DEBUG] C1.R0: Left Right Width Center [DEBUG] B0: 328 384 56 356 [DEBUG] B1: 336 392 56 364 [DEBUG] B2: 344 400 56 372 [DEBUG] B3: 232 288 56 260 [DEBUG] B4: 240 296 56 268 [DEBUG] B5: 256 312 56 284 [DEBUG] B6: 272 328 56 300 [DEBUG] B7: 288 352 64 320 [DEBUG] Step 3: Quarter preamble - Walk backwards [DEBUG] C0: Preamble [DEBUG] B0: 180 [DEBUG] B1: 188 [DEBUG] B2: 204 [DEBUG] B3: 212 [DEBUG] B4: 220 [DEBUG] B5: 228 [DEBUG] B6: 244 [DEBUG] B7: 260 [DEBUG] C1: Preamble [DEBUG] B0: 228 [DEBUG] B1: 236 [DEBUG] B2: 244 [DEBUG] B3: 260 [DEBUG] B4: 268 [DEBUG] B5: 284 [DEBUG] B6: 300 [DEBUG] B7: 320 [DEBUG] Step 4: Add 1 qclk [DEBUG] Step 5: Walk forward to find rising edge [DEBUG] Step 6: center on preamble and clean up rank [DEBUG] C0: Preamble increment [DEBUG] B0: 210 29 [DEBUG] B1: 221 32 [DEBUG] B2: 234 29 [DEBUG] B3: 245 32 [DEBUG] B4: 250 29 [DEBUG] B5: 268 39 [DEBUG] B6: 274 29 [DEBUG] B7: 293 32 [DEBUG] C1: Preamble increment [DEBUG] B0: 258 29 [DEBUG] B1: 273 36 [DEBUG] B2: 284 39 [DEBUG] B3: 293 32 [DEBUG] B4: 306 37 [DEBUG] B5: 321 36 [DEBUG] B6: 333 32 [DEBUG] B7: 355 34 [DEBUG] Rank 1 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C0.R1: Left Right Width Center [DEBUG] B0: 280 336 56 308 [DEBUG] B1: 296 352 56 324 [DEBUG] B2: 304 360 56 332 [DEBUG] B3: 312 368 56 340 [DEBUG] B4: 320 376 56 348 [DEBUG] B5: 328 384 56 356 [DEBUG] B6: 232 288 56 260 [DEBUG] B7: 240 296 56 268 [DEBUG] C1.R1: Left Right Width Center [DEBUG] B0: 216 280 64 248 [DEBUG] B1: 224 280 56 252 [DEBUG] B2: 224 280 56 252 [DEBUG] B3: 232 296 64 264 [DEBUG] B4: 240 296 56 268 [DEBUG] B5: 256 312 56 284 [DEBUG] B6: 280 344 64 312 [DEBUG] B7: 288 344 56 316 [DEBUG] Step 3: Quarter preamble - Walk backwards [DEBUG] C0: Preamble [DEBUG] B0: 180 [DEBUG] B1: 196 [DEBUG] B2: 204 [DEBUG] B3: 212 [DEBUG] B4: 220 [DEBUG] B5: 228 [DEBUG] B6: 260 [DEBUG] B7: 268 [DEBUG] C1: Preamble [DEBUG] B0: 248 [DEBUG] B1: 252 [DEBUG] B2: 252 [DEBUG] B3: 264 [DEBUG] B4: 268 [DEBUG] B5: 284 [DEBUG] B6: 312 [DEBUG] B7: 316 [DEBUG] Step 4: Add 1 qclk [DEBUG] Step 5: Walk forward to find rising edge [DEBUG] Step 6: center on preamble and clean up rank [DEBUG] C0: Preamble increment [DEBUG] B0: 211 30 [DEBUG] B1: 226 29 [DEBUG] B2: 237 32 [DEBUG] B3: 245 32 [DEBUG] B4: 250 29 [DEBUG] B5: 263 34 [DEBUG] B6: 289 28 [DEBUG] B7: 301 32 [DEBUG] C1: Preamble increment [DEBUG] B0: 277 28 [DEBUG] B1: 282 29 [DEBUG] B2: 285 32 [DEBUG] B3: 299 34 [DEBUG] B4: 306 37 [DEBUG] B5: 321 36 [DEBUG] B6: 343 30 [DEBUG] B7: 347 30 [DEBUG] Rank 2 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C0.R2: Left Right Width Center [DEBUG] B0: 288 344 56 316 [DEBUG] B1: 304 360 56 332 [DEBUG] B2: 312 368 56 340 [DEBUG] B3: 320 376 56 348 [DEBUG] B4: 336 392 56 364 [DEBUG] B5: 224 280 56 252 [DEBUG] B6: 232 288 56 260 [DEBUG] B7: 248 304 56 276 [DEBUG] C1.R2: Left Right Width Center [DEBUG] B0: 344 392 48 368 [DEBUG] B1: 224 280 56 252 [DEBUG] B2: 232 288 56 260 [DEBUG] B3: 240 296 56 268 [DEBUG] B4: 248 304 56 276 [DEBUG] B5: 264 320 56 292 [DEBUG] B6: 288 344 56 316 [DEBUG] B7: 296 352 56 324 [DEBUG] Step 3: Quarter preamble - Walk backwards [DEBUG] C0: Preamble [DEBUG] B0: 188 [DEBUG] B1: 204 [DEBUG] B2: 212 [DEBUG] B3: 220 [DEBUG] B4: 236 [DEBUG] B5: 252 [DEBUG] B6: 260 [DEBUG] B7: 276 [DEBUG] C1: Preamble [DEBUG] B0: 240 [DEBUG] B1: 252 [DEBUG] B2: 260 [DEBUG] B3: 268 [DEBUG] B4: 276 [DEBUG] B5: 292 [DEBUG] B6: 316 [DEBUG] B7: 324 [DEBUG] Step 4: Add 1 qclk [DEBUG] Step 5: Walk forward to find rising edge [DEBUG] Step 6: center on preamble and clean up rank [DEBUG] C0: Preamble increment [DEBUG] B0: 224 35 [DEBUG] B1: 235 30 [DEBUG] B2: 243 30 [DEBUG] B3: 254 33 [DEBUG] B4: 268 31 [DEBUG] B5: 282 29 [DEBUG] B6: 291 30 [DEBUG] B7: 310 33 [DEBUG] C1: Preamble increment [DEBUG] B0: 274 33 [DEBUG] B1: 284 31 [DEBUG] B2: 291 30 [DEBUG] B3: 302 33 [DEBUG] B4: 314 37 [DEBUG] B5: 329 36 [DEBUG] B6: 349 32 [DEBUG] B7: 357 32 [DEBUG] Rank 3 [DEBUG] Steps 1 and 2: Find middle of high region [DEBUG] Update RcvEn timing to be in the center of high region [DEBUG] C1.R3: Left Right Width Center [DEBUG] B0: 336 392 56 364 [DEBUG] B1: 224 280 56 252 [DEBUG] B2: 240 296 56 268 [DEBUG] B3: 248 304 56 276 [DEBUG] B4: 256 312 56 284 [DEBUG] B5: 272 320 48 296 [DEBUG] B6: 280 336 56 308 [DEBUG] B7: 304 360 56 332 [DEBUG] Step 3: Quarter preamble - Walk backwards [DEBUG] C1: Preamble [DEBUG] B0: 236 [DEBUG] B1: 252 [DEBUG] B2: 268 [DEBUG] B3: 276 [DEBUG] B4: 284 [DEBUG] B5: 296 [DEBUG] B6: 308 [DEBUG] B7: 332 [DEBUG] Step 4: Add 1 qclk [DEBUG] Step 5: Walk forward to find rising edge [DEBUG] Step 6: center on preamble and clean up rank [DEBUG] C1: Preamble increment [DEBUG] B0: 270 33 [DEBUG] B1: 284 31 [DEBUG] B2: 302 33 [DEBUG] B3: 312 35 [DEBUG] B4: 318 33 [DEBUG] B5: 333 36 [DEBUG] B6: 342 33 [DEBUG] B7: 362 29 [DEBUG] Step 7: Sync IO latency across all ranks [DEBUG] Final Receive Enable and IO latency settings: [DEBUG] C0.R0: IOLAT = 7 rt_iocomp = 23 [DEBUG] B0: 274 [DEBUG] B1: 285 [DEBUG] B2: 298 [DEBUG] B3: 309 [DEBUG] B4: 314 [DEBUG] B5: 332 [DEBUG] B6: 338 [DEBUG] B7: 357 [DEBUG] C0.R1: IOLAT = 7 rt_iocomp = 23 [DEBUG] B0: 275 [DEBUG] B1: 290 [DEBUG] B2: 301 [DEBUG] B3: 309 [DEBUG] B4: 314 [DEBUG] B5: 327 [DEBUG] B6: 353 [DEBUG] B7: 365 [DEBUG] C0.R2: IOLAT = 7 rt_iocomp = 23 [DEBUG] B0: 288 [DEBUG] B1: 299 [DEBUG] B2: 307 [DEBUG] B3: 318 [DEBUG] B4: 332 [DEBUG] B5: 346 [DEBUG] B6: 355 [DEBUG] B7: 374 [DEBUG] C1.R0: IOLAT = 6 rt_iocomp = 23 [DEBUG] B0: 258 [DEBUG] B1: 273 [DEBUG] B2: 284 [DEBUG] B3: 293 [DEBUG] B4: 306 [DEBUG] B5: 321 [DEBUG] B6: 333 [DEBUG] B7: 355 [DEBUG] C1.R1: IOLAT = 6 rt_iocomp = 23 [DEBUG] B0: 277 [DEBUG] B1: 282 [DEBUG] B2: 285 [DEBUG] B3: 299 [DEBUG] B4: 306 [DEBUG] B5: 321 [DEBUG] B6: 343 [DEBUG] B7: 347 [DEBUG] C1.R2: IOLAT = 6 rt_iocomp = 23 [DEBUG] B0: 274 [DEBUG] B1: 284 [DEBUG] B2: 291 [DEBUG] B3: 302 [DEBUG] B4: 314 [DEBUG] B5: 329 [DEBUG] B6: 349 [DEBUG] B7: 357 [DEBUG] C1.R3: IOLAT = 6 rt_iocomp = 23 [DEBUG] B0: 270 [DEBUG] B1: 284 [DEBUG] B2: 302 [DEBUG] B3: 312 [DEBUG] B4: 318 [DEBUG] B5: 333 [DEBUG] B6: 342 [DEBUG] B7: 362 [DEBUG] Rank 0 [DEBUG] C0.R0: Left Right Width Center RxDqsPN [DEBUG] B0: -11 31 42 10 42 [DEBUG] B1: -10 31 41 10 42 [DEBUG] B2: -10 31 41 10 42 [DEBUG] B3: -12 31 43 9 41 [DEBUG] B4: -11 31 42 10 42 [DEBUG] B5: -14 23 37 4 36 [DEBUG] B6: -13 31 44 9 41 [DEBUG] B7: -13 31 44 9 41 [DEBUG] C1.R0: Left Right Width Center RxDqsPN [DEBUG] B0: -14 31 45 8 40 [DEBUG] B1: -14 31 45 8 40 [DEBUG] B2: -13 31 44 9 41 [DEBUG] B3: -15 31 46 8 40 [DEBUG] B4: -15 31 46 8 40 [DEBUG] B5: -15 31 46 8 40 [DEBUG] B6: -14 31 45 8 40 [DEBUG] B7: -15 31 46 8 40 [DEBUG] Rank 1 [DEBUG] C0.R1: Left Right Width Center RxDqsPN [DEBUG] B0: -11 31 42 10 42 [DEBUG] B1: -12 31 43 9 41 [DEBUG] B2: -9 31 40 11 43 [DEBUG] B3: -12 31 43 9 41 [DEBUG] B4: -13 31 44 9 41 [DEBUG] B5: -11 31 42 10 42 [DEBUG] B6: -11 31 42 10 42 [DEBUG] B7: -14 31 45 8 40 [DEBUG] C1.R1: Left Right Width Center RxDqsPN [DEBUG] B0: -13 31 44 9 41 [DEBUG] B1: -10 31 41 10 42 [DEBUG] B2: -13 31 44 9 41 [DEBUG] B3: -16 31 47 7 39 [DEBUG] B4: -14 31 45 8 40 [DEBUG] B5: -13 31 44 9 41 [DEBUG] B6: -10 31 41 10 42 [DEBUG] B7: -12 31 43 9 41 [DEBUG] Rank 2 [DEBUG] C0.R2: Left Right Width Center RxDqsPN [DEBUG] B0: -20 31 51 5 37 [DEBUG] B1: -19 30 49 5 37 [DEBUG] B2: -22 31 53 4 36 [DEBUG] B3: -22 31 53 4 36 [DEBUG] B4: -23 31 54 4 36 [DEBUG] B5: -23 31 54 4 36 [DEBUG] B6: -23 31 54 4 36 [DEBUG] B7: -21 31 52 5 37 [DEBUG] C1.R2: Left Right Width Center RxDqsPN [DEBUG] B0: -15 31 46 8 40 [DEBUG] B1: -13 31 44 9 41 [DEBUG] B2: -12 31 43 9 41 [DEBUG] B3: -14 31 45 8 40 [DEBUG] B4: -14 31 45 8 40 [DEBUG] B5: -15 31 46 8 40 [DEBUG] B6: -14 31 45 8 40 [DEBUG] B7: -14 31 45 8 40 [DEBUG] Rank 3 [DEBUG] C1.R3: Left Right Width Center RxDqsPN [DEBUG] B0: -12 31 43 9 41 [DEBUG] B1: -15 31 46 8 40 [DEBUG] B2: -13 31 44 9 41 [DEBUG] B3: -14 31 45 8 40 [DEBUG] B4: -12 31 43 9 41 [DEBUG] B5: -15 31 46 8 40 [DEBUG] B6: -14 31 45 8 40 [DEBUG] B7: -16 31 47 7 39 [DEBUG] Rank 0 [DEBUG] InitSt InitEn CurrSt CurrEn LargSt LargEn [DEBUG] C0 [DEBUG] B0: 192 260 318 388 318 388 [DEBUG] B1: 190 190 198 260 198 260 [DEBUG] B2: 190 190 212 272 212 272 [DEBUG] B3: 190 190 242 310 242 310 [DEBUG] B4: 190 190 252 316 252 316 [DEBUG] B5: 192 208 268 336 268 336 [DEBUG] B6: 192 220 280 348 280 348 [DEBUG] B7: 192 230 290 358 290 358 [DEBUG] C1 [DEBUG] B0: 192 250 316 378 316 378 [DEBUG] B1: 190 190 204 274 204 274 [DEBUG] B2: 190 190 224 290 224 290 [DEBUG] B3: 190 190 240 308 240 308 [DEBUG] B4: 192 196 256 324 256 324 [DEBUG] B5: 192 212 272 340 272 340 [DEBUG] B6: 192 214 270 342 270 342 [DEBUG] B7: 192 218 280 346 280 346 [DEBUG] C0.R0: LftEdge Width [DEBUG] B0: 318 70 [DEBUG] B1: 198 62 [DEBUG] B2: 212 60 [DEBUG] B3: 242 68 [DEBUG] B4: 252 64 [DEBUG] B5: 268 68 [DEBUG] B6: 280 68 [DEBUG] B7: 290 68 [DEBUG] C1.R0: LftEdge Width [DEBUG] B0: 316 62 [DEBUG] B1: 204 70 [DEBUG] B2: 224 66 [DEBUG] B3: 240 68 [DEBUG] B4: 256 68 [DEBUG] B5: 272 68 [DEBUG] B6: 270 72 [DEBUG] B7: 280 66 [DEBUG] Rank 1 [DEBUG] InitSt InitEn CurrSt CurrEn LargSt LargEn [DEBUG] C0 [DEBUG] B0: 190 190 198 266 198 266 [DEBUG] B1: 190 190 208 276 208 276 [DEBUG] B2: 190 190 220 280 220 280 [DEBUG] B3: 190 190 242 310 242 310 [DEBUG] B4: 192 202 262 330 262 330 [DEBUG] B5: 192 192 260 320 260 320 [DEBUG] B6: 192 220 284 348 284 348 [DEBUG] B7: 192 230 290 358 290 358 [DEBUG] C1 [DEBUG] B0: 192 256 316 384 316 384 [DEBUG] B1: 190 190 206 266 206 266 [DEBUG] B2: 190 190 222 282 222 282 [DEBUG] B3: 190 190 240 306 240 306 [DEBUG] B4: 190 190 256 316 256 316 [DEBUG] B5: 192 194 262 322 262 322 [DEBUG] B6: 192 202 272 330 272 330 [DEBUG] B7: 192 222 288 350 288 350 [DEBUG] C0.R1: LftEdge Width [DEBUG] B0: 198 68 [DEBUG] B1: 208 68 [DEBUG] B2: 220 60 [DEBUG] B3: 242 68 [DEBUG] B4: 262 68 [DEBUG] B5: 260 60 [DEBUG] B6: 284 64 [DEBUG] B7: 290 68 [DEBUG] C1.R1: LftEdge Width [DEBUG] B0: 316 68 [DEBUG] B1: 206 60 [DEBUG] B2: 222 60 [DEBUG] B3: 240 66 [DEBUG] B4: 256 60 [DEBUG] B5: 262 60 [DEBUG] B6: 272 58 [DEBUG] B7: 288 62 [DEBUG] Rank 2 [DEBUG] InitSt InitEn CurrSt CurrEn LargSt LargEn [DEBUG] C0 [DEBUG] B0: 192 266 318 394 318 394 [DEBUG] B1: 190 190 210 284 210 284 [DEBUG] B2: 190 190 224 298 224 298 [DEBUG] B3: 190 190 240 314 240 314 [DEBUG] B4: 192 210 262 338 262 338 [DEBUG] B5: 192 222 274 350 274 350 [DEBUG] B6: 192 230 284 358 284 358 [DEBUG] B7: 192 234 290 362 290 362 [DEBUG] C1 [DEBUG] B0: 190 190 206 274 206 274 [DEBUG] B1: 190 190 210 278 210 278 [DEBUG] B2: 190 190 220 282 220 282 [DEBUG] B3: 190 190 252 312 252 312 [DEBUG] B4: 192 206 266 334 266 334 [DEBUG] B5: 192 218 280 346 280 346 [DEBUG] B6: 192 212 274 340 274 340 [DEBUG] B7: 192 210 278 338 278 338 [DEBUG] C0.R2: LftEdge Width [DEBUG] B0: 318 76 [DEBUG] B1: 210 74 [DEBUG] B2: 224 74 [DEBUG] B3: 240 74 [DEBUG] B4: 262 76 [DEBUG] B5: 274 76 [DEBUG] B6: 284 74 [DEBUG] B7: 290 72 [DEBUG] C1.R2: LftEdge Width [DEBUG] B0: 206 68 [DEBUG] B1: 210 68 [DEBUG] B2: 220 62 [DEBUG] B3: 252 60 [DEBUG] B4: 266 68 [DEBUG] B5: 280 66 [DEBUG] B6: 274 66 [DEBUG] B7: 278 60 [DEBUG] Rank 3 [DEBUG] InitSt InitEn CurrSt CurrEn LargSt LargEn [DEBUG] C1 [DEBUG] B0: 190 190 206 268 206 268 [DEBUG] B1: 190 190 214 284 214 284 [DEBUG] B2: 190 190 230 298 230 298 [DEBUG] B3: 190 190 244 306 244 306 [DEBUG] B4: 190 190 258 318 258 318 [DEBUG] B5: 192 212 280 340 280 340 [DEBUG] B6: 192 218 286 346 286 346 [DEBUG] B7: 192 228 290 356 290 356 [DEBUG] C1.R3: LftEdge Width [DEBUG] B0: 206 62 [DEBUG] B1: 214 70 [DEBUG] B2: 230 68 [DEBUG] B3: 244 62 [DEBUG] B4: 258 60 [DEBUG] B5: 280 60 [DEBUG] B6: 286 60 [DEBUG] B7: 290 66 [DEBUG] Rank 0 [DEBUG] C0.R0: Offset FinalEdge [DEBUG] B0: -128 190 [DEBUG] B1: 0 198 [DEBUG] B2: 0 212 [DEBUG] B3: 0 242 [DEBUG] B4: 0 252 [DEBUG] B5: 0 268 [DEBUG] B6: 0 280 [DEBUG] B7: 0 290 [DEBUG] C1.R0: Offset FinalEdge [DEBUG] B0: -128 188 [DEBUG] B1: 0 204 [DEBUG] B2: 0 224 [DEBUG] B3: 0 240 [DEBUG] B4: 0 256 [DEBUG] B5: 0 272 [DEBUG] B6: 0 270 [DEBUG] B7: 0 280 [DEBUG] Rank 1 [DEBUG] C0.R1: Offset FinalEdge [DEBUG] B0: 0 198 [DEBUG] B1: 0 208 [DEBUG] B2: 0 220 [DEBUG] B3: 0 242 [DEBUG] B4: 0 262 [DEBUG] B5: 0 260 [DEBUG] B6: 0 284 [DEBUG] B7: 0 290 [DEBUG] C1.R1: Offset FinalEdge [DEBUG] B0: -128 188 [DEBUG] B1: 0 206 [DEBUG] B2: 0 222 [DEBUG] B3: 0 240 [DEBUG] B4: 0 256 [DEBUG] B5: 0 262 [DEBUG] B6: 0 272 [DEBUG] B7: 0 288 [DEBUG] Rank 2 [DEBUG] C0.R2: Offset FinalEdge [DEBUG] B0: -128 190 [DEBUG] B1: 0 210 [DEBUG] B2: 0 224 [DEBUG] B3: 0 240 [DEBUG] B4: 0 262 [DEBUG] B5: 0 274 [DEBUG] B6: 0 284 [DEBUG] B7: 0 290 [DEBUG] C1.R2: Offset FinalEdge [DEBUG] B0: 0 206 [DEBUG] B1: 0 210 [DEBUG] B2: 0 220 [DEBUG] B3: 0 252 [DEBUG] B4: 0 266 [DEBUG] B5: 0 280 [DEBUG] B6: 0 274 [DEBUG] B7: 0 278 [DEBUG] Rank 3 [DEBUG] C1.R3: Offset FinalEdge [DEBUG] B0: 0 206 [DEBUG] B1: 0 214 [DEBUG] B2: 0 230 [DEBUG] B3: 0 244 [DEBUG] B4: 0 258 [DEBUG] B5: 0 280 [DEBUG] B6: 0 286 [DEBUG] B7: 0 290 [DEBUG] Waiting for mc_init_done acknowledgement... DONE! [DEBUG] memcfg DDR3 clock 1333 MHz [DEBUG] memcfg channel assignment: A: 1, B 0, C 2 [DEBUG] memcfg channel[0] config (00621020): [DEBUG] ECC inactive [DEBUG] enhanced interleave mode on [DEBUG] rank interleave on [DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected [DEBUG] DIMMB 4096 MB width x8 or x32 single rank [DEBUG] memcfg channel[1] config (00662020): [DEBUG] ECC inactive [DEBUG] enhanced interleave mode on [DEBUG] rank interleave on [DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected [DEBUG] DIMMB 8192 MB width x8 or x32 dual rank [DEBUG] ME: Requested 0MB UMA [DEBUG] ME: FW Partition Table : OK [DEBUG] ME: Bringup Loader Failure : NO [DEBUG] ME: Firmware Init Complete : NO [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: Boot Options Present : NO [DEBUG] ME: Update In Progress : NO [DEBUG] ME: Current Working State : Initializing [DEBUG] ME: Current Operation State : Bring up [DEBUG] ME: Current Operation Mode : Debug [DEBUG] ME: Error Code : No Error [DEBUG] ME: Progress Phase : BUP Phase [DEBUG] ME: Power Management Event : Clean Moff->Mx wake [DEBUG] ME: Progress Phase State : 0x4d [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x7f7ff000 254 entries. [DEBUG] IMD: root @ 0x7f7fec00 62 entries. [DEBUG] Starting cbfs_boot_device [DEBUG] FMAP: area RW_MRC_CACHE found @ 400000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [DEBUG] flash size 0x2800000 bytes [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000 [ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. [DEBUG] SF: Successfully written 2 bytes @ 0x400008 [DEBUG] SF: Successfully written 20 bytes @ 0x403080 [DEBUG] SF: Successfully written 4108 bytes @ 0x403094 [DEBUG] MRC: updated 'RW_MRC_CACHE'. [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0x7f800000 0x800000 [DEBUG] Subregion 0: 0x7f800000 0x300000 [DEBUG] Subregion 1: 0x7fb00000 0x100000 [DEBUG] Subregion 2: 0x7fc00000 0x400000 [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/postcar' @0x4a2c0 size 0x5aa8 in mcache @0xff7e1064 [DEBUG] Loading module at 0x7f7ce000 with entry 0x7f7ce031. filesize: 0x5748 memsize: 0xba70 [DEBUG] Processing 200 relocs. Offset value of 0x7d7ce000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 2490 ms [NOTE ] coreboot-26.01rev1 Mon Sep 21 21:28:52 UTC 2026 x86_32 postcar starting (log level: 7)... [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/ramstage' @0x29040 size 0x1d510 in mcache @0x7f7dd0ec [DEBUG] Loading module at 0x7f684000 with entry 0x7f684000. filesize: 0x39400 memsize: 0x1485f0 [DEBUG] Processing 4135 relocs. Offset value of 0x7b684000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 37 ms [NOTE ] coreboot-26.01rev1 Mon Sep 21 21:28:52 UTC 2026 x86_32 ramstage starting (log level: 7)... [DEBUG] Normal boot [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 00000000 enabled [DEBUG] DOMAIN: 00000000 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 00 [DEBUG] PCI: 00:00:00.0 [8086/0c00] enabled [DEBUG] PCI: 00:00:01.0 [8086/0c01] enabled [DEBUG] PCI: 00:00:02.0 [8086/041e] enabled [DEBUG] PCI: 00:00:03.0 [8086/0c0c] enabled [DEBUG] PCI: 00:00:14.0 [8086/8c31] enabled [DEBUG] PCI: 00:00:16.0 [8086/8c3a] enabled [DEBUG] PCI: 00:00:16.1: Disabling device [DEBUG] PCI: 00:00:16.2: Disabling device [INFO ] PCI: Static device PCI: 00:00:16.3 not found, disabling it. [DEBUG] PCI: 00:00:19.0 [8086/153a] enabled [DEBUG] PCI: 00:00:1a.0 [8086/8c2d] enabled [DEBUG] PCI: 00:00:1b.0 [8086/8c20] enabled [DEBUG] PCI: 00:00:1c.0 [8086/8c10] disabled [DEBUG] PCI: 00:00:1c.1 [8086/8c12] disabled [DEBUG] PCI: 00:00:1c.2 [8086/8c14] disabled [DEBUG] PCI: 00:00:1c.3 [8086/8c16] disabled [DEBUG] Adjusted number of PCIe root ports to 5 as per strpfusecfg2 [DEBUG] PCIe Root Port 5 ASPM is disabled [DEBUG] PCI: 00:00:1c.0: Disabling device [DEBUG] PCI: 00:00:1c.1: Disabling device [DEBUG] PCI: 00:00:1c.2: Disabling device [DEBUG] PCI: 00:00:1c.3: Disabling device [DEBUG] PCH: PCIe map 1c.4 -> 1c.0 [DEBUG] PCH: PCIe map 1c.0 -> 1c.1 [DEBUG] PCH: PCIe map 1c.1 -> 1c.2 [DEBUG] PCH: PCIe map 1c.2 -> 1c.3 [DEBUG] PCH: PCIe map 1c.3 -> 1c.4 [DEBUG] PCI: 00:00:1c.0 [8086/8c18] enabled [DEBUG] PCI: 00:00:1d.0 [8086/8c26] enabled [DEBUG] PCI: 00:00:1f.0 [8086/8c4e] enabled [DEBUG] PCI: 00:00:1f.2 [8086/8c00] enabled [DEBUG] PCI: 00:00:1f.3 [8086/8c22] enabled [DEBUG] PCI: 00:00:1f.5: Disabling device [DEBUG] PCI: 00:00:1f.5 [8086/8c08] disabled [DEBUG] PCI: 00:00:1f.6: Disabling device [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:00:16.1 [WARN ] PCI: 00:00:16.2 [WARN ] PCI: 00:00:16.3 [WARN ] PCI: 00:00:1c.5 [WARN ] PCI: 00:00:1c.6 [WARN ] PCI: 00:00:1c.7 [WARN ] PCI: 00:00:1f.6 [WARN ] PCI: Check your devicetree.cb. [DEBUG] PCI: 00:00:01.0 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 01 [INFO ] PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:01.0 finished in 14 msecs [DEBUG] PCI: 00:00:1c.0 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 02 [INFO ] PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port [DEBUG] scan_bus: bus PCI: 00:00:1c.0 finished in 14 msecs [DEBUG] PCI: 00:00:1f.0 scanning... [DEBUG] PNP: 002e.0 enabled [DEBUG] PNP: 002e.1 enabled [DEBUG] PNP: 002e.7 enabled [DEBUG] PNP: 002e.8 disabled [DEBUG] PNP: 002e.c enabled [DEBUG] PNP: 002e.a enabled [DEBUG] PNP: 002e.b disabled [DEBUG] PNP: 002e.11 disabled [INFO ] Found TPM 1.2 ST33ZP24 (0x0000) by ST Microelectronics (0x104a) [DEBUG] PNP: 0c31.0 enabled [DEBUG] scan_bus: bus PCI: 00:00:1f.0 finished in 37 msecs [DEBUG] PCI: 00:00:1f.3 scanning... [DEBUG] scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 303 msecs [DEBUG] scan_bus: bus Root Device finished in 320 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 335 ms [DEBUG] found VGA at PCI: 00:00:02.0 [DEBUG] Setting up VGA for PCI: 00:00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. [DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. [DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. [DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. [DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. [DEBUG] MC MAP: TOM: 0x700000000 [DEBUG] MC MAP: TOUUD: 0x77be00000 [DEBUG] MC MAP: MESEG_BASE: 0x7ffff00000 [DEBUG] MC MAP: MESEG_LIMIT: 0xfffff [DEBUG] MC MAP: REMAP_BASE: 0x700000000 [DEBUG] MC MAP: REMAP_LIMIT: 0x77bdfffff [DEBUG] MC MAP: TOLUD: 0x84200000 [DEBUG] MC MAP: BGSM: 0x80000000 [DEBUG] MC MAP: BDSM: 0x80200000 [DEBUG] MC MAP: TSEGMB: 0x7f800000 [DEBUG] MC MAP: GGC: 0x211 [DEBUG] MC MAP: DPR: 0x7f800001 [INFO ] Available memory above 4GB: 26558M [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) === [INFO ] === Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed) [DEBUG] avoid_fixed_resources: PNP: 002e.0 60 base 00000a00 limit 00000a0f io (fixed) [DEBUG] avoid_fixed_resources: PNP: 002e.1 60 base 00000060 limit 00000060 io (fixed) [DEBUG] avoid_fixed_resources: PNP: 002e.7 60 base 000003f8 limit 000003ff io (fixed) [DEBUG] avoid_fixed_resources: PNP: 002e.c 60 base 0000002e limit 0000002f io (fixed) [DEBUG] avoid_fixed_resources: PNP: 002e.a 60 base 00000a40 limit 00000a7f io (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 1000, Size: f000, Tag: 100 [DEBUG] PCI: 00:00:02.0 20 * [0xffc0 - 0xffff] limit: ffff io [DEBUG] PCI: 00:00:19.0 18 * [0xffa0 - 0xffbf] limit: ffbf io [DEBUG] PCI: 00:00:1f.2 20 * [0xff80 - 0xff9f] limit: ff9f io [DEBUG] PCI: 00:00:1f.2 10 * [0xff78 - 0xff7f] limit: ff7f io [DEBUG] PCI: 00:00:1f.2 18 * [0xff70 - 0xff77] limit: ff77 io [DEBUG] PCI: 00:00:1f.2 14 * [0xff6c - 0xff6f] limit: ff6f io [DEBUG] PCI: 00:00:1f.2 1c * [0xff68 - 0xff6b] limit: ff6b io [DEBUG] DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 48 base fed10000 limit fed17fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 68 base fed18000 limit fed18fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 40 base fed19000 limit fed19fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5420 base fed84000 limit fed84fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 5408 base fed80000 limit fed83fff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 00 base 00000000 limit 0009ffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 01 base 000a0000 limit 000bffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 02 base 000c0000 limit 000fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 03 base 00100000 limit 7f7fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 04 base 7f800000 limit 7fffffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 05 base 80000000 limit 841fffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:00.0 06 base 100000000 limit 77bdfffff mem (fixed) [DEBUG] avoid_fixed_resources: PCI: 00:00:1f.0 31fe base fec00000 limit ffffffff mem (fixed) [DEBUG] avoid_fixed_resources: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) [INFO ] DOMAIN: 00000000: Resource ranges: [INFO ] * Base: 84200000, Size: 6be00000, Tag: 200 [INFO ] * Base: 77be00000, Size: 7884200000, Tag: 200 [DEBUG] PCI: 00:00:02.0 18 * [0xe0000000 - 0xefffffff] limit: efffffff prefmem [DEBUG] PCI: 00:00:02.0 10 * [0xdfc00000 - 0xdfffffff] limit: dfffffff mem [DEBUG] PCI: 00:00:19.0 10 * [0xdfbe0000 - 0xdfbfffff] limit: dfbfffff mem [DEBUG] PCI: 00:00:14.0 10 * [0xdfbd0000 - 0xdfbdffff] limit: dfbdffff mem [DEBUG] PCI: 00:00:03.0 10 * [0xdfbcc000 - 0xdfbcffff] limit: dfbcffff mem [DEBUG] PCI: 00:00:1b.0 10 * [0xdfbc8000 - 0xdfbcbfff] limit: dfbcbfff mem [DEBUG] PCI: 00:00:19.0 14 * [0xdfbc7000 - 0xdfbc7fff] limit: dfbc7fff mem [DEBUG] PCI: 00:00:1f.2 24 * [0xdfbc6000 - 0xdfbc67ff] limit: dfbc67ff mem [DEBUG] PCI: 00:00:1a.0 10 * [0xdfbc5000 - 0xdfbc53ff] limit: dfbc53ff mem [DEBUG] PCI: 00:00:1d.0 10 * [0xdfbc4000 - 0xdfbc43ff] limit: dfbc43ff mem [DEBUG] PCI: 00:00:1f.3 10 * [0xdfbc3000 - 0xdfbc30ff] limit: dfbc30ff mem [DEBUG] PCI: 00:00:16.0 10 * [0xdfbc2000 - 0xdfbc200f] limit: dfbc200f mem [DEBUG] DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff done [DEBUG] DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done [INFO ] === Resource allocator: DOMAIN: 00000000 - resource allocation complete === [DEBUG] PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io [DEBUG] PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem [DEBUG] PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem [DEBUG] PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64 [DEBUG] PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64 [DEBUG] PCI: 00:00:02.0 20 <- [0x000000000000ffc0 - 0x000000000000ffff] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:00:03.0 10 <- [0x00000000dfbcc000 - 0x00000000dfbcffff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:14.0 10 <- [0x00000000dfbd0000 - 0x00000000dfbdffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:00:16.0 10 <- [0x00000000dfbc2000 - 0x00000000dfbc200f] size 0x00000010 gran 0x04 mem64 [DEBUG] PCI: 00:00:19.0 10 <- [0x00000000dfbe0000 - 0x00000000dfbfffff] size 0x00020000 gran 0x11 mem [DEBUG] PCI: 00:00:19.0 14 <- [0x00000000dfbc7000 - 0x00000000dfbc7fff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:00:19.0 18 <- [0x000000000000ffa0 - 0x000000000000ffbf] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:00:1a.0 10 <- [0x00000000dfbc5000 - 0x00000000dfbc53ff] size 0x00000400 gran 0x0a mem [DEBUG] PCI: 00:00:1b.0 10 <- [0x00000000dfbc8000 - 0x00000000dfbcbfff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 02 io [DEBUG] PCI: 00:00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 prefmem [DEBUG] PCI: 00:00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 02 mem [DEBUG] PCI: 00:00:1d.0 10 <- [0x00000000dfbc4000 - 0x00000000dfbc43ff] size 0x00000400 gran 0x0a mem [DEBUG] PCI: 00:00:1f.2 10 <- [0x000000000000ff78 - 0x000000000000ff7f] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:00:1f.2 14 <- [0x000000000000ff6c - 0x000000000000ff6f] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:00:1f.2 18 <- [0x000000000000ff70 - 0x000000000000ff77] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:00:1f.2 1c <- [0x000000000000ff68 - 0x000000000000ff6b] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:00:1f.2 20 <- [0x000000000000ff80 - 0x000000000000ff9f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:00:1f.2 24 <- [0x00000000dfbc6000 - 0x00000000dfbc67ff] size 0x00000800 gran 0x0b mem [DEBUG] PCI: 00:00:1f.3 10 <- [0x00000000dfbc3000 - 0x00000000dfbc30ff] size 0x00000100 gran 0x08 mem64 [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 1 / 813 ms [INFO ] Enabling resources... [DEBUG] PCI: 00:00:00.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:00.0 cmd <- 06 [DEBUG] PCI: 00:00:01.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:01.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:01.0 cmd <- 00 [DEBUG] PCI: 00:00:02.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:02.0 cmd <- 03 [DEBUG] PCI: 00:00:03.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:03.0 cmd <- 02 [DEBUG] PCI: 00:00:14.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:14.0 cmd <- 102 [DEBUG] PCI: 00:00:16.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:16.0 cmd <- 02 [DEBUG] PCI: 00:00:19.0 subsystem <- 1028/05a4 [DEBUG] PCI: 00:00:19.0 cmd <- 103 [DEBUG] PCI: 00:00:1a.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1a.0 cmd <- 106 [DEBUG] PCI: 00:00:1b.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1b.0 cmd <- 102 [DEBUG] PCI: 00:00:1c.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:00:1c.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1c.0 cmd <- 00 [DEBUG] PCI: 00:00:1d.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1d.0 cmd <- 106 [DEBUG] PCI: 00:00:1f.0 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1f.0 cmd <- 107 [DEBUG] PCI: 00:00:1f.2 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1f.2 cmd <- 103 [DEBUG] PCI: 00:00:1f.3 subsystem <- 1028/05a5 [DEBUG] PCI: 00:00:1f.3 cmd <- 103 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 138 ms [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6 [DEBUG] 0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0 [DEBUG] 0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1 [DEBUG] 0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0 [DEBUG] 0x0000000100000000 - 0x000000077bdfffff size 0x67be00000 type 6 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] apic_id 0x0 setup mtrr for CPU physical address size: 39 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 4/5. [DEBUG] MTRR: WB selected as default type. [DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0 [DEBUG] MTRR: 1 base 0x00000000c0000000 mask 0x0000007fe0000000 type 0 [DEBUG] MTRR: 2 base 0x00000000e0000000 mask 0x0000007ff0000000 type 1 [DEBUG] MTRR: 3 base 0x00000000f0000000 mask 0x0000007ff0000000 type 0 [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled [DEBUG] Initializing VR config. [DEBUG] CPU has 2 cores, 4 threads enabled. [DEBUG] Setting up SMI for CPU [INFO ] Will perform SMM setup. [DEBUG] microcode: sig=0x306c3 pf=0x2 revision=0x28 [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0xf800 in mcache @0x7f7dd02c [INFO ] CPU: Intel(R) Core(TM) i3-4150 CPU @ 3.50GHz. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] CPU: APIC: 02 enabled [DEBUG] CPU: APIC: 03 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [INFO ] LAPIC 0x1 in XAPIC mode. [DEBUG] done. [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000028 [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x2 in XAPIC mode. [INFO ] LAPIC 0x3 in XAPIC mode. [INFO ] AP: slot 2 apic_id 2, MCU rev: 0x00000028 [INFO ] AP: slot 3 apic_id 3, MCU rev: 0x00000028 [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0 [DEBUG] Processing 9 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0x7f801000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f6a4264 [DEBUG] Installing permanent SMM handler to 0x7f800000 [DEBUG] HANDLER [0x7fafe000-0x7faff76f] [DEBUG] CPU 0 [DEBUG] ss0 [0x7fafdc00-0x7fafdfff] [DEBUG] stub0 [0x7faf6000-0x7faf619f] [DEBUG] CPU 1 [DEBUG] ss1 [0x7fafd800-0x7fafdbff] [DEBUG] stub1 [0x7faf5c00-0x7faf5d9f] [DEBUG] CPU 2 [DEBUG] ss2 [0x7fafd400-0x7fafd7ff] [DEBUG] stub2 [0x7faf5800-0x7faf599f] [DEBUG] CPU 3 [DEBUG] ss3 [0x7fafd000-0x7fafd3ff] [DEBUG] stub3 [0x7faf5400-0x7faf559f] [DEBUG] stacks [0x7f800000-0x7f800fff] [DEBUG] Loading module at 0x7fafe000 with entry 0x7fafe725. filesize: 0x1710 memsize: 0x1770 [DEBUG] Processing 65 relocs. Offset value of 0x7fafe000 [DEBUG] Loading module at 0x7faf6000 with entry 0x7faf6000. filesize: 0x1a0 memsize: 0x1a0 [DEBUG] Processing 9 relocs. Offset value of 0x7faf6000 [DEBUG] smm_module_setup_stub: stack_top = 0x7f801000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000 [DEBUG] SMM Module: placing smm entry code at 7faf5c00, cpu # 0x1 [DEBUG] SMM Module: placing smm entry code at 7faf5800, cpu # 0x2 [DEBUG] SMM Module: placing smm entry code at 7faf5400, cpu # 0x3 [DEBUG] SMM Module: stub loaded at 7faf6000. Will call 0x7fafe725 [DEBUG] SMI_STS: PM1 [DEBUG] WAK PWRBTN TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faee000, cpu = 0 [DEBUG] In relocation handler: CPU 0 [DEBUG] New SMBASE=0x7faee000 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faedc00, cpu = 1 [DEBUG] In relocation handler: CPU 1 [DEBUG] New SMBASE=0x7faedc00 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed400, cpu = 3 [DEBUG] In relocation handler: CPU 3 [DEBUG] New SMBASE=0x7faed400 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed800, cpu = 2 [DEBUG] In relocation handler: CPU 2 [DEBUG] New SMBASE=0x7faed800 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] cpu: energy policy set to 6 [INFO ] Turbo is unavailable [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [INFO ] Initializing CPU #2 [INFO ] Initializing CPU #3 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #2 initialized [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #3 initialized [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL status: locked [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #1 initialized [INFO ] bsp_do_flight_plan done after 437 msecs. [DEBUG] CPU: frequency set to 3500 [DEBUG] Enabling SMIs. [DEBUG] Locking SMM. [DEBUG] MTRR: TEMPORARY Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6 [DEBUG] 0x0000000080000000 - 0x00000000ff7fffff size 0x7f800000 type 0 [DEBUG] 0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5 [DEBUG] 0x0000000100000000 - 0x000000077bdfffff size 0x67be00000 type 6 [DEBUG] MTRR: default type WB/UC MTRR counts: 9/5. [DEBUG] MTRR: UC selected as default type. [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 [DEBUG] MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 5 [DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6 [DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000007e00000000 type 6 [DEBUG] MTRR: 4 base 0x0000000400000000 mask 0x0000007c00000000 type 6 [DEBUG] CPU_CLUSTER: 0 init finished in 834 msecs [DEBUG] PCI: 00:00:00.0 init [DEBUG] Disabling PEG12. [DEBUG] Disabling PEG11. [DEBUG] Disabling "device 4". [DEBUG] Disabling "device 7". [DEBUG] Set BIOS_RESET_CPL [DEBUG] CPU TDP: 54 Watts [DEBUG] PCI: 00:00:00.0 init finished in 20 msecs [DEBUG] PCI: 00:00:01.0 init [DEBUG] PCI: 00:00:01.0 init finished in 0 msecs [DEBUG] PCI: 00:00:02.0 init [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'vbt.bin' @0x497c0 size 0x5a3 in mcache @0x7f7dd1e4 [INFO ] Found a VBT of 4409 bytes [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [DEBUG] GT Power Management Init [INFO ] framebuffer_info: bytes_per_line: 15360, bits_per_pixel: 32 [INFO ] x_res x y_res: 3840 x 2160, size: 33177600 at 0xe0000000 [DEBUG] GT Power Management Init (post VBIOS) [DEBUG] PCI: 00:00:02.0 init finished in 554 msecs [DEBUG] PCI: 00:00:03.0 init [DEBUG] Mini-HD: base = 0xdfbcc000 [DEBUG] azalia_audio: initializing codec #0... [DEBUG] azalia_audio: - vendor/device id: 0x80862807 [DEBUG] azalia_audio: - verb size: 16 [DEBUG] azalia_audio: - verb loaded [DEBUG] PCI: 00:00:03.0 init finished in 26 msecs [DEBUG] PCI: 00:00:14.0 init [DEBUG] PCI: 00:00:14.0 init finished in 0 msecs [DEBUG] PCI: 00:00:16.0 init [DEBUG] ME: FW Partition Table : OK [DEBUG] ME: Bringup Loader Failure : NO [DEBUG] ME: Firmware Init Complete : NO [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: Boot Options Present : NO [DEBUG] ME: Update In Progress : NO [DEBUG] ME: Current Working State : Initializing [DEBUG] ME: Current Operation State : Bring up [DEBUG] ME: Current Operation Mode : Debug [DEBUG] ME: Error Code : No Error [DEBUG] ME: Progress Phase : BUP Phase [DEBUG] ME: Power Management Event : Clean Moff->Mx wake [DEBUG] ME: Progress Phase State : 0x4d [CRIT ] intel_me_path: mbp is not ready! [NOTE ] ME: BIOS path: Error [ERROR] ME: MBP not ready [DEBUG] PCI: 00:00:16.0 init finished in 72 msecs [DEBUG] PCI: 00:00:19.0 init [DEBUG] PCI: 00:00:19.0 init finished in 0 msecs [DEBUG] PCI: 00:00:1a.0 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:00:1a.0 init finished in 4 msecs [DEBUG] PCI: 00:00:1b.0 init [DEBUG] Azalia: base = 0xdfbc8000 [DEBUG] Azalia: codec_mask = 01 [DEBUG] azalia_audio: initializing codec #0... [DEBUG] azalia_audio: - vendor/device id: 0x10ec0280 [DEBUG] azalia_audio: - verb size: 52 [DEBUG] azalia_audio: - verb loaded [DEBUG] PCI: 00:00:1b.0 init finished in 32 msecs [DEBUG] PCI: 00:00:1c.0 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:00:1c.0 init finished in 4 msecs [DEBUG] PCI: 00:00:1d.0 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:00:1d.0 init finished in 4 msecs [DEBUG] PCI: 00:00:1f.0 init [DEBUG] pch: lpc_init [DEBUG] IOAPIC: Initializing IOAPIC at fec00000 [DEBUG] IOAPIC: ID = 0x00 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at fec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [INFO ] Set power off after power failure. [INFO ] NMI sources disabled. [DEBUG] LynxPoint H PM init [DEBUG] RTC: failed = 0x0 [DEBUG] RTC Init [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] PCI: 00:00:1f.0 init finished in 48 msecs [DEBUG] PCI: 00:00:1f.2 init [DEBUG] SATA: Initializing... [DEBUG] SATA: Controller in AHCI mode. [DEBUG] ABAR: 0xdfbc6000 [DEBUG] PCI: 00:00:1f.2 init finished in 10 msecs [DEBUG] PCI: 00:00:1f.3 init [DEBUG] PCI: 00:00:1f.3 init finished in 0 msecs [DEBUG] PNP: 002e.0 init [DEBUG] PNP: 002e.0 init finished in 0 msecs [DEBUG] PNP: 002e.1 init [DEBUG] PNP: 002e.1 init finished in 0 msecs [DEBUG] PNP: 002e.7 init [DEBUG] PNP: 002e.7 init finished in 0 msecs [DEBUG] PNP: 002e.c init [DEBUG] PNP: 002e.c init finished in 0 msecs [DEBUG] PNP: 002e.a init [DEBUG] PNP: 002e.a init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 735 / 1052 ms [DEBUG] TPM: Startup [DEBUG] TPM: command 0x99 returned 0x0 [DEBUG] TPM: Asserting physical presence [DEBUG] TPM: command 0x4000000a returned 0x0 [DEBUG] TPM: command 0x65 returned 0x0 [DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1 [INFO ] TPM: setup succeeded [DEBUG] clear_memory: Clearing DRAM 0000000000000000-0000000000005000 [ERROR] Null dereference at eip: 0x7f6a867d [DEBUG] clear_memory: Clearing DRAM 000000000000a000-00000000000a0000 [DEBUG] clear_memory: Clearing DRAM 00000000000c0000-000000007f66f000 [DEBUG] clear_memory: Clearing DRAM 000000007f800000-0000000080000000 [DEBUG] clear_memory: Clearing DRAM 0000000100000000-000000077be00000 [DEBUG] memset_pae: Using virtual address 0x00400000 as scratchpad [DEBUG] init_pae_pagetables: Using address 0x00005000 for page tables [DEBUG] clear_memory: Clearing DRAM 0000000000005000-000000000000a000 [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 2016 / 89 ms [INFO ] Finalize devices... [DEBUG] PCI: 00:00:00.0 final [DEBUG] PCI: 00:00:16.0 final [INFO ] ME: MBP cleared [DEBUG] PCI: 00:00:1b.0 final [DEBUG] PCI: 00:00:1f.0 final [DEBUG] flash size 0x2800000 bytes [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2800000 [ERROR] SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [INFO ] Devices finalized [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 48 ms [DEBUG] OptiPlex 9020 late HWM init [DEBUG] GPIO chassis type = 0xd [DEBUG] Chassis type = 0x6 [DEBUG] Temp target = 0x81 [DEBUG] Package power = 0x10 [DEBUG] BS: BS_POST_DEVICE exit times (exec / console): 8 / 17 ms [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x47640 size 0x2125 in mcache @0x7f7dd1b8 [DEBUG] Starting cbfs_boot_device [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at 7f643000. [DEBUG] ACPI: * FACS [DEBUG] ACPI: * FACP [DEBUG] ACPI: added table 1/32, length now 44 [DEBUG] Found 1 CPU(s) with 4 core(s) each. [DEBUG] PSS: 3500MHz power 54000 control 0x2300 status 0x2300 [DEBUG] PSS: 2800MHz power 39787 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 32477 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 25777 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 19619 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 13943 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 8815 control 0x800 status 0x800 [DEBUG] PSS: 3500MHz power 54000 control 0x2300 status 0x2300 [DEBUG] PSS: 2800MHz power 39787 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 32477 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 25777 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 19619 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 13943 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 8815 control 0x800 status 0x800 [DEBUG] PSS: 3500MHz power 54000 control 0x2300 status 0x2300 [DEBUG] PSS: 2800MHz power 39787 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 32477 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 25777 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 19619 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 13943 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 8815 control 0x800 status 0x800 [DEBUG] PSS: 3500MHz power 54000 control 0x2300 status 0x2300 [DEBUG] PSS: 2800MHz power 39787 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 32477 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 25777 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 19619 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 13943 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 8815 control 0x800 status 0x800 [DEBUG] Generating ACPI PIRQ entries [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0 [DEBUG] ACPI: * SSDT [DEBUG] ACPI: added table 2/32, length now 52 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 60 [DEBUG] TCPA log created at 0x7f633000 [DEBUG] ACPI: * TCPA [DEBUG] ACPI: added table 4/32, length now 68 [DEBUG] IOAPIC: 24 interrupts [DEBUG] ACPI: * APIC [DEBUG] ACPI: added table 5/32, length now 76 [DEBUG] ACPI: * SPCR [DEBUG] ACPI: added table 6/32, length now 84 [DEBUG] current = 7f646a90 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 7/32, length now 92 [DEBUG] current = 7f646ad0 [INFO ] ACPI: done. [DEBUG] ACPI tables: 15056 bytes. [DEBUG] smbios_write_tables: 7f62b000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '26.01rev1' [INFO ] Create SMBIOS type 16 [INFO ] Create SMBIOS type 17 [INFO ] Create SMBIOS type 20 [DEBUG] SMBIOS tables: 1351 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 1078 [DEBUG] Writing coreboot table at 0x7f667000 [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'cmos_layout.bin' @0x49f00 size 0x35c in mcache @0x7f7dd23c [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000f5fff: RESERVED [DEBUG] 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES [DEBUG] 4. 00000000000f7000-00000000000fffff: RESERVED [DEBUG] 5. 0000000000100000-000000007f62afff: RAM [DEBUG] 6. 000000007f62b000-000000007f683fff: CONFIGURATION TABLES [DEBUG] 7. 000000007f684000-000000007f7ccfff: RAMSTAGE [DEBUG] 8. 000000007f7cd000-000000007f7fffff: CONFIGURATION TABLES [DEBUG] 9. 000000007f800000-00000000841fffff: RESERVED [DEBUG] 10. 00000000f0000000-00000000f3ffffff: RESERVED [DEBUG] 11. 00000000fed10000-00000000fed19fff: RESERVED [DEBUG] 12. 00000000fed40000-00000000fed44fff: RESERVED [DEBUG] 13. 00000000fed80000-00000000fed84fff: RESERVED [DEBUG] 14. 0000000100000000-000000077bdfffff: RAM [DEBUG] Starting cbfs_boot_device [DEBUG] Wrote coreboot table at: 0x7f667000, 0x7ac bytes, checksum f702 [DEBUG] coreboot table: 1988 bytes. [DEBUG] IMD ROOT 0. 0x7f7ff000 0x00001000 [DEBUG] IMD SMALL 1. 0x7f7fe000 0x00001000 [DEBUG] CONSOLE 2. 0x7f7de000 0x00020000 [DEBUG] RO MCACHE 3. 0x7f7dd000 0x000003d8 [DEBUG] TIME STAMP 4. 0x7f7dc000 0x00000910 [DEBUG] MEM INFO 5. 0x7f7da000 0x000010c8 [DEBUG] AFTER CAR 6. 0x7f7cd000 0x0000d000 [DEBUG] RAMSTAGE 7. 0x7f683000 0x0014a000 [DEBUG] SMM BACKUP 8. 0x7f673000 0x00010000 [DEBUG] IGD OPREGION 9. 0x7f66f000 0x00003200 [DEBUG] COREBOOT 10. 0x7f667000 0x00008000 [DEBUG] ACPI 11. 0x7f643000 0x00024000 [DEBUG] TCPA TCGLOG12. 0x7f633000 0x00010000 [DEBUG] SMBIOS 13. 0x7f62b000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x7f7fec00 0x00000400 [DEBUG] FMAP 1. 0x7f7feb20 0x000000e0 [DEBUG] ROMSTAGE 2. 0x7f7feb00 0x00000004 [DEBUG] ROMSTG STCK 3. 0x7f7fea40 0x000000a8 [DEBUG] ACPI GNVS 4. 0x7f7fe980 0x000000b0 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 1 / 540 ms [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/payload' @0x4fdc0 size 0x11b60 in mcache @0x7f7dd2a8 [DEBUG] Checking segment from ROM address 0xff860dec [DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable. [DEBUG] Checking segment from ROM address 0xff860e08 [DEBUG] Loading segment from ROM address 0xff860dec [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x000de2a0 memsize 0x21d60 srcaddr 0xff860e24 filesize 0x11b28 [DEBUG] Loading Segment: addr: 0x000de2a0 memsz: 0x0000000000021d60 filesz: 0x0000000000011b28 [DEBUG] using LZMA [DEBUG] Loading segment from ROM address 0xff860e08 [DEBUG] Entry Point 0x000fd253 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 7 / 69 ms [DEBUG] ICH-NM10-PCH: watchdog disabled [DEBUG] Jumping to boot code at 0x000fd253(0x7f667000)